The invention relates to a rapidly resettable counting device comprising a counter which is clocked by a clock signal.
There are many uses requiring accurately clocked counters capable of resetting rapidly, i.e. counters which after a reset operation proceed with counting upon the next clock pulse. Such counters are required, for example, for processing digital television signals, or for digital signal processors.
In known digital signal processors the counting devices generally require a latency time of several clock periods. Consequently, a reset operation will take effect only after several clock pulses. This problem can be circumvented by arranging a plurality of slow sub-counters in parallel, which counters operate at one n.sup.th of the clock frequency, n being the number of sub-counters. However, it is then difficult and therefore expensive to achieve that the sub-counters are reset with the correct time and phase relationship.
It is an object of the invention to provide a rapidly resettable counting device which does not have these problems.